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TECH.REF
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1994-01-28
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Technical Reference
CONEX 6.3a
Fri 01-28-94 10:35:14
╒══════════════════════════════════════════════════════════════════════╕
│ Ports │
╘══════════════════════════════════════════════════════════════════════╛
COM
────────────────────────────────────────────────────────────────────
- by default COM 1/3 use interrupt 4, COM 2/4 use interrupt 3
- base port registers are read from BIOS communication area
normally 03f8h is COM 1 and 02f8h is COM 2
port *F8 - Transmit/Receive Buffer (read/write)
Baud Rate Divisor LSB if bit 7 of LCR is set (read/write)
port *F9 - Interrupt Enable Register - IER (read/write)
Baud Rate Divisor MSB if bit 7 of LCR is set (read/write)
│7│6│5│4│3│2│1│0│
│ │ │ └──── 1 = enable data available int
│ │ └───── 1 = enable THRE interrupt
│ └────── 1 = enable lines status interrupt
└─────── 1 = enable modem-status-change interrupt
Baud Rate Divisor Table
Baud Rate Baud Rate
Baud Rate Divisor Baud Rate Divisor
50 2304 2400 48
75 1536 3600 32
110 1047 4800 24
150 768 9600 12
200 576 14400 8
300 384 19200 6
600 192 38400 3
1200 96 57600 2
1800 64 115200 1
port *FA - Interrupt Identification Register - IIR (read only)
│7│6│5│4│3│2│1│0│ 2FA, 3FA Interrupt ID Register
│ │ │ │ │ │ │ └──── 1 = no int. pending, 0=int. pending
│ │ │ │ │ └─┴───── Interrupt Id bits (see below)
│ │ │ │ └──────── 16550 1 = timeout int. pending, 0 for 8250/16450
│ │ └─┴───────── reserved (zero)
└─┴──────────── 16550 set to 1 if FIFO queues are enabled
Bits
21 description Priority To reset
00 modem-status-change lowest read MSR
01 transmit-register-empty low read IIR / write THR
10 data-available high read rec buffer reg
11 line-status highest read LSR
- interrupt pending flag uses reverse logic, 0 = pending, 1 = none
- interrupt will occur if any of the line status bits are set
- THRE bit is set when THRE register is emptied into the TSR
Port *FA - 16550 FIFO Control Register - FCR (write only)
│7│6│5│4│3│2│1│0│ 2FA, 3FA FIFO Control Register
│ │ │ │ │ │ │ └──── 1 = enable clear XMIT and RCVR FIFO queues
│ │ │ │ │ │ └───── 1 = clear RCVR FIFO
│ │ │ │ │ └────── 1 = clear XMIT FIFO
│ │ │ │ └─────── 1 = change RXRDY & TXRDY pins from mode 0 to mode 1
│ │ └─┴──────── reserved (zero)
└─┴─────────── trigger level for RCVR FIFO interrupt
Bits RCVR FIFO
76 Trigger Level
00 1 byte
01 4 bytes
10 8 bytes
11 14 bytes
- Bit 0 must be set in order to write to other FCR bits
- Bit 1 when set to 1 the RCVR FIFO is cleared and this bit is reset.
The receiver shift register is not cleared.
- Bit 2 when set to 1 the XMIT FIFO is cleared and this bit is reset.
The transmit shift register is not cleared.
port *FB - Line Control Register - LCR (read/write)
│7│6│5│4│3│2│1│0│
│ │ │ │ │ │ └─┴──── word length select bits (see below)
│ │ │ │ │ └─────── 0 = 1 stop bit, 1 = 1.5 or 2 (see note)
│ │ │ │ └──────── 0 = no parity, 1 = parity (PEN)
│ │ │ └───────── 0 = odd parity, 1 = even (EPS)
│ │ └────────── 0 = parity disabled, 1 = enabled
│ └─────────── 0 = turn break off, 1 = force spacing break state
└──────────── 1 = baud rate divisor (DLAB)
Bits
10 Word length bits
00 = 5 bits per character
01 = 6 bits per character
10 = 7 bits per character
11 = 8 bits per character
port *FC - Modem Control Register - MCR (read/write)
│7│6│5│4│3│2│1│0│
│ │ │ └──── 1 = activate DTR
│ │ └───── 1 = activate RTS
│ └────── OUT1
└─────── OUT2
port *FD - Line Status Register - LSR (read only)
│7│6│5│4│3│2│1│0│
│ │ │ │ │ │ └──── 1 = data ready
│ │ │ │ │ └───── 1 = overrun error (OE)
│ │ │ │ └────── 1 = parity error (PE)
│ │ │ └─────── 1 = framing error (FE)
│ │ └──────── 1 = break interrupt (BI)
│ └───────── 1 = transmitter holding register empty (THRE)
└────────── 1 = transmitter shift register empty (TSRE)
port *FE - Modem Status Register - MSR (read only)
│7│6│5│4│3│2│1│0│
│ │ │ │ │ │ │ └──── 1 = DCTS Delta CTS (CTS changed)
│ │ │ │ │ │ └───── 1 = DDSR Delta DSR (DSR changed)
│ │ │ │ │ └────── 1 = RI ring indicator changed
│ │ │ │ └─────── 1 = DDCD Delta Data Carrier Detect (DCD changed)
│ │ │ └──────── 1 = CTS
│ │ └───────── 1 = DSR
│ └────────── 1 = ring indicator (RI)
└─────────── 1 = receive line signal detect
INT 14H
────────────────────────────────────────────────────────────────────
INT 14,0 - Initialize Communications Port Parameters
AH = 00
AL = parms for initialization (see tables below)
DX = zero based serial port number (0-1) (0-3 for AT)
│7│6│5│4│3│2│1│0│ AL Parity (bits 4 & 3)
│ │ │ │ │ │ └─┴──── word length bits 00 = none
│ │ │ │ │ └─────── stop bits flag 01 = odd
│ │ │ └─┴──────── parity bits 10 = none
└─┴─┴─────────── baud rate bits 11 = even
Word length (bits 1 & 0) Stop bit count (bit 2)
10 = 7 bits 0 = 1 stop bit
11 = 8 bits 1 = 2 stop bits
Baud rate (bits 7, 6 & 5)
000 = 110 baud 100 = 1200 baud
001 = 150 baud 101 = 2400 baud
010 = 300 baud 110 = 4800 baud
011 = 600 baud 111 = 9600 baud
on return:
AH = port status
AL = modem status
INT 14,1 - Send Character to Communications Port
AH = 01
AL = character to send
DX = zero based serial port number (0-1) (0-3 for AT)
on return:
AH = port status
bit 7=0 indicates success
bit 7=1 indicates error, bits 0-6 indicate cause
INT 14,2 - Receive Character from Communications Port
AH = 02
DX = zero based serial port number (0-1) (0-3 for AT)
on return:
AH = port status
bit 7 = 0 if successful
bit 7 = 1 if call failed
AL = character received if call was success
INT 14,3 - Get Serial Port Status
AH = 03
DX = zero based serial port number (0-1) (0-3 for AT)
on return:
AH = port status
AL = modem status
INT 14,4 - Send Break (not part of BIOS)
AH = 04
╒══════════════════════════════════════════════════════════════════════╕
│ VT320 Commands │
╘══════════════════════════════════════════════════════════════════════╛
- VT100 commands are marked with (1)
Cursor movement
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